In order to obtain a semiconductor device having a finer structure, a dual damascene method has been employed as a multilayer wiring technique. Further, in response to requests for miniaturization of a semiconductor device and for a high operating speed, a technique has been developed whereby a CVD film, which is formed by doping an oxide film with an organic group, or an inorganic or organic film, which is formed by coating, is employed to reduce the dielectric constant (k) of an interlayer insulating film, thereby reducing the transmission of an electric signal.
FIG. 13 is a cross-sectional view of a conventional semiconductor device having a low-k dielectric film. In FIG. 13, a low-k dielectric film 602 is deposited on a substrate 601 having a diffusion layer 601a, and a multilayer wiring structure having a plurality of laminated wirings 604 and vias 603 are provided in the low-k dielectric film 602. A bonding pad 605 is formed at a predetermined location on the topmost wiring 604, and a wire 606 is connected to the bonding pad 605.
The multi-functionality of a semiconductor device is accelerated as the low-k dielectric film 602 is introduced, and the number of bonding pads 605 used for the input/output of electric signals is increased. And as the ratio of the area occupied by the bonding pads 605 in the semiconductor device is increased, there is a corresponding accelerated reduction in the pitch and the size of the bonding pads 605. FIG. 14 is a plan view for explaining the intervals and the sizes of bonding pads. As shown in FIG. 14, a pad size 128 is reduced from a conventional 100 square μm or larger to 80 square μm or 60 square μm, and a currently obtained pad interval 129 is only about 5 μm, while conventionally it was 10 μm or longer. Therefore, the size of a pad pitch is reduced, and the joint area for the bonding pad and the wire is reduced.
According to an advanced semiconductor device that employs both a wire bonding technique for reducing pad pitch, and a low-k dielectric film for providing a finer structure and a higher operating speed, stress or impact occurred in wire bonding would be concentrated in the small bonding pads 605. Therefore, as shown in FIG. 13, a crack 607 may occur under the bonding pad 605, or the surface of the low-k dielectric film 602 may peel off the bonding pad 605 at the boundary between the low-k dielectric film 602 and the bonding pad 605. The cracking in the low-k dielectric film 602 or the peeling off of its surface would result not only in a bonding failure or an interruption in the transmission of electric signals, but would also, by adsorbing water, induce the corrosion of wiring and excessively deteriorate the reliability of the semiconductor device. Further, copper wiring 604, located under the bonding pad 605, would be exposed, and oxidization of the copper wiring 604 would occur. Thus, the characteristic of adhesion between the oxidized copper film and the bonding pad 605 would be reduced, and the wire bonding strength would be reduced.
In order to resolve these shortcomings, there has been proposed that laminated metallic films are used for bonding pads to increase both the resistance of an electrode portion and the interconnection of layers to resist the shocks that occur in wire bonding (see, for example, Japanese Patent Laid-Open Publication No. H11-340319). This method is effective when a bonding pad having a satisfactory size can be obtained. However, when this method is employed together with a pitch reduction technique that stress and shock are concentrated in a small area, the thin films used to form the bonding pad may peel off during bonding because of the laminated structure of such a bonding pad. Therefore, this method cannot cope with a reduction in the pad pitch, a currently desired improvement. And further, since the manufacturing method and the procedure management method are complicated, it is highly probable that stable mass production would be difficult.
On the other hand, there has been proposed that a structure having a higher shock resistance than an interlayer insulating film material layer is placed under a bonding pad to reinforce layers underlying the bonding pad (see, for example, Japanese Patent Laid-Open Publication No. H11-54544). FIG. 15 is a cross-sectional view of a conventional semiconductor having reinforced wirings.
However, the reinforced structure is independent from the signal wirings in the above-mentioned semiconductor device, and the reinforced wirings underlying the bonding pad are not acted as a device. Therefore, there are problems that a die size is enlarged by the size of the reinforced wirings and that the size of the semiconductor chip cannot be reduced.